It is well known in the art that high ignition voltage loads, such as gas discharge lamps, commonly operate in a starting mode, an operating or steady state mode, and a restrike mode. During the starting mode, a relatively higher starting voltage or ignition voltage is required across electrodes of the gas discharge lamp to first place the gases of the lamp into a suitable ionized condition for initiating a glow breakdown state.
Prior art ignitor circuits generally include a pulse transformer with a separate firing circuit capable of producing a high voltage pulse and a drive circuit controlling an H-bridge or a 1/2 bridge connected to the gas discharge lamp. The 1/2 bridge comprises two (2) transistors, such as field effect transistors (FETs), only one of which is "on" at any given moment of operation. Simultaneous "on" states of the two FETs is guarded against in the prior art circuits to prevent damage to the circuit.
During the starting mode, an initial high voltage pulse is generated by the pulse transformer and firing circuit and applied to the gas discharge lamp. After the starting mode, and during the operation or conduction mode, a relatively lower voltage is applied across the gas discharge lamp through the FETs which are alternatively turned on and off.
However, the firing circuit is only operational during the relatively brief ignition mode and is dormant otherwise. Thus, there is no need for the firing circuit except during the ignition mode. The firing circuit requires precise control both as to the duration of its operation and its coordination with the driving circuit, which may be difficult to achieve because the firing circuit is separate from the driving circuit. Thus, a deficiency in the prior art is the inefficient implementation of a distinct firing circuit and the corresponding hardware to achieve its precise control.
Accordingly, there is a need in the art for an improved ignition circuit for high ignition voltage resonant loads which permits the elimination of a distinct firing circuit and a corresponding reduction of the associated hardware.